Digital signals
A digital signal has two levels only: 1 (high), e.g. 5 V, and 0 (low), e.g. 0 V. Noise that changes 5 V to 4.6 V does not change the meaning, so digital signals can be copied and processed without errors piling up.
Combinational logic
In combinational logic the output depends only on the inputs at that moment. Basic gates:
- NOT: output is the opposite of the input.
- AND: 1 only if all inputs are 1.
- OR: 1 if any input is 1.
- NAND, NOR: AND and OR followed by NOT.
- XOR: 1 if the inputs are different.
A truth table lists the output for every input combination. With n inputs there are 2ⁿ rows. Gates can be combined; NAND alone (or NOR alone) can build any other gate. Combinational systems include decoders, adders and the logic in a burglar alarm.
Boolean expressions
We write AND as A·B, OR as A + B and NOT as Ā. Example: Y = (A·B) + C̄.
Sequential logic
In sequential logic the output depends on the inputs and on the previous state. It needs memory. The basic memory cell is the flip-flop (a bistable: it has two stable states).
D-type flip-flop
Inputs D (data) and clock; output Q. On the rising edge of the clock, Q becomes equal to D. Between edges Q does not change, whatever D does. So it stores one bit.
Counters and dividers
If a D flip-flop's Q̄ output is fed back to D, Q toggles on every clock pulse: the output frequency is half the clock frequency (a divide-by-2). Chaining 3 such stages gives a 3-bit binary counter (0 to 7); n stages count to 2ⁿ − 1. Decade counters count 0–9 and reset, used in clocks and displays.
Shift registers
Flip-flops in a line, each passing its bit to the next on each clock, move data along: used to turn serial data into parallel data.
Astables
A bistable has two stable states; a monostable has one; an astable has none: it keeps switching between high and low by itself, giving a square or rectangular wave. This is the clock for sequential logic.
Period: T = t_high + t_low, frequency f = 1/T. The mark-space ratio is t_high : t_low.
A common astable is built with a 555 timer IC, a capacitor and two resistors. The capacitor charges and discharges, and the times depend on R × C: bigger R or C → slower clock. For a 555 astable, t_high ≈ 0.7(R₁ + R₂)C and t_low ≈ 0.7R₂C.
Try it: a paper flip-flop
Write 0 on one side of a coin-sized paper and 1 on the other. Only flip it when someone claps (the clock). Between claps, ignore all shouting (D changes). You are a flip-flop! Now in the 3D, press Clock pulse 5 times and check the lamps show 101.
Key formulas and definitions
- Rows in a truth table = 2ⁿ (n inputs)
- f = 1 / T, T = t_high + t_low
- Mark-space ratio = t_high : t_low
- n-stage counter counts 0 to 2ⁿ − 1; each stage halves the frequency
- 555 astable: t_high ≈ 0.7(R₁ + R₂)C, t_low ≈ 0.7R₂C
Worked examples
1. Write the truth table of a 2-input NAND gate.
00 → 1, 01 → 1, 10 → 1, 11 → 0. (AND, then NOT.)
2. How many rows does a truth table for 4 inputs have?
2⁴ = 16 rows.
3. Y = A·B + C. Find Y for A = 1, B = 0, C = 1.
A·B = 0; 0 + 1 = 1. Y = 1.
4. An astable is high for 3 ms and low for 1 ms. Find f and the mark-space ratio.
T = 4 ms; f = 1/0.004 = 250 Hz. Mark-space = 3:1.
5. A 1 kHz clock drives a chain of 4 divide-by-2 flip-flops. What is the output frequency of the last stage?
1000 / 2⁴ = 62.5 Hz.
6. A 3-bit counter starts at 000. What does it show after 11 clock pulses?
Counts wrap after 8: 11 − 8 = 3, so 011.
7. A 555 astable has R₁ = 10 kΩ, R₂ = 20 kΩ, C = 10 μF. Find t_high, t_low and f.
t_high = 0.7 × 30 000 × 10⁻⁵ = 0.21 s; t_low = 0.7 × 20 000 × 10⁻⁵ = 0.14 s; T = 0.35 s; f ≈ 2.9 Hz.
Common mistakes
- Mixing up OR and XOR: for inputs 1,1, OR gives 1 but XOR gives 0.
- Thinking a D flip-flop copies D at any time. It only changes on the clock edge.
- Forgetting that a counter wraps round: a 3-bit counter goes 111 → 000.
- Using f = T instead of f = 1/T, or forgetting to add t_high and t_low.