The processor and its components
- ALU (arithmetic logic unit): does arithmetic (add, subtract), logic (AND, OR, NOT, XOR), shifts and comparisons.
- Control unit (CU): decodes instructions and sends control signals to coordinate the other parts.
- Clock: sends regular pulses; each step happens on a tick. Clock speed is measured in hertz (for example 3 GHz = 3 billion ticks per second).
- Registers: tiny, very fast stores inside the CPU.
- PC (program counter): address of the next instruction.
- MAR (memory address register): address to read from or write to.
- MDR (memory data register, or MBR): data just read or about to be written.
- CIR (current instruction register): the instruction being decoded and executed.
- ACC (accumulator) or general-purpose registers: hold working values and results.
- Status register: flags such as zero, negative, carry, overflow and interrupt enable.
- Buses: the address bus (one way, CPU → memory), the data bus (two way) and the control bus (signals like read, write, clock, interrupt request).
The fetch–decode–execute cycle
Written in register transfer notation ([ ] means 'contents of'):
- MAR ← [PC]: copy the address of the next instruction into MAR.
- PC ← [PC] + 1: PC now points at the following instruction.
- MDR ← [Memory]addressed: the instruction is read along the data bus into MDR.
- CIR ← [MDR]: copy the instruction to CIR.
- Decode: the CU splits the instruction into opcode (what to do) and operand (what to do it to).
- Execute: for example load a value into ACC, use the ALU, store a result, or change PC for a branch.
- Check for interrupts, then repeat.
Instruction sets and addressing modes
An instruction set is the complete list of machine instructions a particular processor can run; each processor family has its own. A machine-code instruction has an opcode (which includes the basic operation and the addressing mode) and one or more operands.
- Immediate addressing: the operand is the value. ADD #3 adds 3.
- Direct addressing: the operand is a memory address. ADD 10 adds whatever is stored at address 10.
Example: if address 10 holds 7, then ADD #10 adds 10 but ADD 10 adds 7.
Assembly language operations
Assembly language uses short mnemonics that map one-to-one onto machine code. Typical operations (shown in a common style):
- LDR Rd, <memory> load; STR Rd, <memory> store; MOV Rd, #n copy a value.
- ADD / SUB Rd, Rn, <operand> arithmetic.
- CMP Rn, <operand> compare (sets status flags); B branch always; BEQ / BNE / BGT / BLT branch if equal, not equal, greater, less.
- AND, ORR, EOR, MVN logical operations; LSL, LSR logical shifts (multiply or divide by 2); HALT.
Selection and loops are written with CMP and conditional branches to labels.
Factors affecting processor performance
- Number of cores: more cores can run more instructions at once, but only if the task can be split into parallel parts.
- Cache memory: small, fast memory on the chip holding recently or often used data; bigger cache means fewer slow trips to RAM.
- Clock speed: more cycles per second means more instructions per second (but more heat).
- Word length: the number of bits processed as one unit; longer words handle bigger numbers in one go.
- Address bus width: n lines can address 2ⁿ memory locations.
- Data bus width: more lines move more bits per transfer.
Interrupts and saving the volatile environment
An interrupt is a signal to the processor that something needs attention: a key press, a timer, a printer out of paper, a hardware fault, or a software error.
- The processor finishes the current fetch–execute cycle, then checks for interrupts.
- If one is waiting and has a higher priority than the current task, the volatile environment (PC, registers, status flags) is pushed onto a stack.
- The PC is loaded with the address of the right interrupt service routine (ISR), often found through an interrupt vector table.
- The ISR runs (it may itself be interrupted by a higher-priority interrupt).
- The saved values are popped back from the stack and the original program continues exactly where it stopped.
Key formulas and definitions
- MAR ← [PC]
- PC ← [PC] + 1; MDR ← [Memory]addressed
- CIR ← [MDR]
- Addressable locations = 2^(address bus width)
- Instructions per second ≈ clock speed × instructions per cycle × cores (ideal)
- Immediate: ADD #n uses n. Direct: ADD n uses Memory[n].
Worked examples
1. Describe what happens in each register during the fetch stage.
PC holds the address of the next instruction; it is copied to MAR. The instruction at that address travels on the data bus to MDR, and PC is incremented. The instruction is then copied from MDR to CIR, ready for decoding.
2. Address 20 holds 5 and the accumulator holds 2. Give ACC after (a) ADD #20 (b) ADD 20.
(a) Immediate: ACC = 2 + 20 = 22. (b) Direct: ACC = 2 + Memory[20] = 2 + 5 = 7.
3. How many memory locations can a 24-bit address bus address?
2²⁴ = 16,777,216 locations (16 Mi).
4. Trace: MOV R0, #4 / ADD R0, R0, #6 / CMP R0, #10 / BEQ done / MOV R0, #0 / done: HALT.
R0 = 4, then 10. CMP sets the zero flag because R0 = 10. BEQ jumps to done, so MOV R0, #0 is skipped. The program halts with R0 = 10.
5. Why must the volatile environment be saved when an interrupt happens?
The ISR will use the same registers and change PC. Without saving PC, registers and flags, the original program could not resume at the right place with the right values.
6. Doubling the cores does not double the speed of a program. Why?
Only parts of the program that can run in parallel benefit; the rest runs on one core. Cores also share cache and memory bandwidth and must coordinate, which costs time.
Common mistakes
- Saying MAR holds data. MAR holds an address; MDR holds the data.
- Forgetting that PC is incremented during fetch, before the instruction executes.
- Mixing up immediate and direct: # means the number itself.
- Saying an interrupt stops the current instruction halfway. It is checked at the end of a cycle.